In HDL design (such as Verilog or VHDL), an active-low reset means the reset signal is enabled when it is low (logic 0). It is widely used in both ASIC and FPGA designs for several practical and electrical reasons:
1. Electrical Stability
- Logic low (0 volts, GND) is generally more stable and noise-immune than logic high (VCC).
- During power-up, signals tend to default to low due to internal pull-downs or the absence of a valid voltage, so using an active-low reset ensures that the system starts in a known, reset state.
2. Better Noise Immunity
- External signals (like buttons or long PCB traces) are often susceptible to electrical noise.
- An active-low signal is less likely to be falsely triggered by noise, especially when combined with pull-up resistors.
3. Compatibility with Open-Drain/Open-Collector Designs
- Active-low resets work well with open-drain or open-collector outputs, which can safely pull the line low.
- This allows multiple devices to share the same reset line and assert reset without conflict.
4. Industry Convention
- Many standard IP cores, microcontrollers, and FPGAs use active-low resets by convention.
- Using active-low ensures compatibility and consistency across designs.
5. Synthesis and Tool Support
- Most EDA tools and synthesis libraries expect or recommend using active-low reset (
reset_n). - Many templates, standard cells, and FPGA primitives are optimized for this.
Example in Verilog
always @(posedge clk or negedge reset_n) begin
if (!reset_n)
state <= IDLE;
else
state <= next_state;
endHere, the reset signal reset_n is active when low, and resets the system when it is 0.
Summary
Active-low reset is used because it is more electrically stable, noise-immune, compatible with shared lines, and widely supported in the industry.