EasyFPGA

Custom RTL Design: TX & RX This is the first hands-on RTL episode. We translate the UART protocol specification directly into synthesizable SystemVerilog — starting from the mathematical relationship between clock frequency and baud rate, then building the TX FSM and RX center-sampling logic. Each design decision is derived from first principles so you can reproduce and modify it for any FPGA or baud rate. Design Requirements Target: 50 MHz system clock, 8E1 format ...

UART Implementation Methods FPGA engineers implementing UART face three choices — each suited to a different project context and level of control. Choosing the wrong approach wastes time: a vendor IP that cannot be customized, or a full processor SoC for a task that needs only a 100-line state machine. This episode provides the decision framework and maps the course structure to each approach. Three Approaches to UART on FPGA ┌─────────────────────────────────────────────────────────┐ │ UART on FPGA — 3 Methods │ ├─────────────────┬──────────────────┬────────────────────┤ │ Method 1 │ Method 2 │ Method 3 │ │ Vendor IP Core │ Soft Processor │ Custom RTL │ │ │ + UART IP │ Design │ ├─────────────────┼──────────────────┼────────────────────┤ │ Easy & fast │ Software-driven │ Full control │ │ AXI-compatible │ Highly scalable │ Best performance │ │ Limited flex │ High resources │ Longer dev time │ └─────────────────┴──────────────────┴────────────────────┘ Method 1: Vendor IP Core Use a verified UART IP from Xilinx/Intel — add via IP Catalog with a few clicks ...

RS-232 & RS-485 When FPGAs communicate with external devices over UART, the signal rarely stays at 3.3V CMOS all the way to the destination. RS-232 defines an electrical standard for single-ended serial links up to 15 m, while RS-485 uses differential signaling to reach 1,200 m on a multi-drop bus. The most important lesson of this episode: UART is a logical protocol, and RS-232/RS-485 are completely separate physical standards that FPGA GPIO cannot directly drive. ...

UART Frame Format Each UART transmission carries data inside a precisely defined frame. Understanding the purpose of every field — not just its name — is what separates a developer who can implement UART from scratch from one who only configures a vendor IP. This episode dissects the frame bit by bit, covering the transmission order convention, parity computation, and the overhead implications of different format choices. UART Frame Structure Every UART transmission is based on a fixed Frame structure. ...

What is UART? UART — Universal Asynchronous Receiver/Transmitter A hardware communication protocol for serial communication between two devices. UART is one of the oldest digital communication protocols still in active use. Despite being designed alongside early teletype systems, it appears in virtually every FPGA board, microcontroller, and development kit — because it needs only two wires and every terminal emulator on every operating system speaks it. This episode covers the fundamentals: what asynchronous communication really means, how baud rate works, and why clock drift is the central engineering challenge when implementing UART from scratch. ...

CRC (Cyclic Redundancy Check) is the most widely used error-detection mechanism in digital communication — from Ethernet frames to USB packets to SSD data integrity. This post explains how CRC works mathematically and shows how to use the free online CRC Calculator & RTL Generator to produce ready-to-simulate SystemVerilog code for your FPGA design. What Is CRC? CRC appends a checksum to a data block so the receiver can detect corruption. The transmitter computes a CRC value over the data and appends it; the receiver recomputes the CRC and compares. A mismatch means a transmission error occurred. ...

Overview As parallel interfaces push to higher speeds, keeping all data bits synchronized becomes increasingly difficult. This post explains why global clock distribution hits a wall — and how source-synchronous signaling solves it. Signal Propagation on PCB Before diving into timing, it helps to understand how fast signals actually travel on a PCB: Typical propagation speed on FR4: 15–17 cm/ns A 1 cm trace length difference ≈ 60–70 ps of timing skew At 1 GHz (1 ns period), 70 ps of skew already consumes 7% of your entire timing budget from a single centimeter of mismatch. As data rates climb, this becomes unmanageable. ...

1. What Is a Parallel Interface? A parallel interface transmits multiple bits simultaneously across multiple data lines. As shown below, there are 8 to 32 or more data wires (D[7:0], D[31:0], etc.) between transmitter and receiver, along with a shared clock and control signals such as VALID and READY. ┌─────────────┐ ┌─────────────┐ │ Transmitter │ D[7:0] │ Receiver │ │ ├────────►│ │ │ │ CLK │ │ │ ├────────►│ │ │ │ VALID │ │ │ ├────────►│ │ └─────────────┘ └─────────────┘ Parallel Bus — 8 data bits transferred simultaneously each clock cycle ■ CLK ■ D[7:0] data ■ VALID Advantages: ...

In FPGA and RTL development, four terms are frequently used to describe code changes: refactor, refine, fix/correct, and optimize. They are often used interchangeably in casual conversation, but they mean distinctly different things. Using the right term helps your team understand immediately what kind of change is being made — and whether to expect any behavioural differences. Refactor Definition: Restructure internal implementation without changing externally observable behaviour. A refactored module passes the same test vectors before and after the change. Simulation output is bit-identical. Timing may or may not improve. ...

An FPGA does not work in isolation. No matter how correct your RTL is, the design will fail if the power supply is noisy, the clock does not reach the device cleanly, or a digital interface is mismatched at the board level. FPGA engineers who can diagnose hardware problems are significantly more effective than those who can only debug RTL in simulation. This post covers the board-level skills that separate a junior FPGA engineer from a senior one. ...