EasyFPGA

Overview As parallel interfaces push to higher speeds, keeping all data bits synchronized becomes increasingly difficult. This post explains why global clock distribution hits a wall — and how source-synchronous signaling solves it. Signal Propagation on PCB Before diving into timing, it helps to understand how fast signals actually travel on a PCB: Typical propagation speed on FR4: 15–17 cm/ns A 1 cm trace length difference ≈ 60–70 ps of timing skew At 1 GHz (1 ns period), 70 ps of skew already consumes 7% of your entire timing budget from a single centimeter of mismatch. As data rates climb, this becomes unmanageable. ...

1. What Is a Parallel Interface? A parallel interface transmits multiple bits simultaneously across multiple data lines. As shown below, there are 8 to 32 or more data wires (D[7:0], D[31:0], etc.) between transmitter and receiver, along with a shared clock and control signals such as VALID and READY. ┌─────────────┐ ┌─────────────┐ │ Transmitter │ D[7:0] │ Receiver │ │ ├────────►│ │ │ │ CLK │ │ │ ├────────►│ │ │ │ VALID │ │ │ ├────────►│ │ └─────────────┘ └─────────────┘ Parallel Bus — 8 data bits transferred simultaneously each clock cycle ■ CLK ■ D[7:0] data ■ VALID Advantages: ...

In FPGA and RTL development, four terms are frequently used to describe code changes: refactor, refine, fix/correct, and optimize. They are often used interchangeably in casual conversation, but they mean distinctly different things. Using the right term helps your team understand immediately what kind of change is being made — and whether to expect any behavioural differences. Refactor Definition: Restructure internal implementation without changing externally observable behaviour. A refactored module passes the same test vectors before and after the change. Simulation output is bit-identical. Timing may or may not improve. ...

An FPGA does not work in isolation. No matter how correct your RTL is, the design will fail if the power supply is noisy, the clock does not reach the device cleanly, or a digital interface is mismatched at the board level. FPGA engineers who can diagnose hardware problems are significantly more effective than those who can only debug RTL in simulation. This post covers the board-level skills that separate a junior FPGA engineer from a senior one. ...

When selecting an AMD/Xilinx FPGA you must specify three attributes beyond logic capacity and memory size: Speed Grade, Temperature Range, and Reliability Grade. Understanding all three helps you choose the right device — and avoid paying for more than you need. AMD UltraScale+ Device Ordering Information (Product Selection Guide) Speed Grade Speed Grade is a post-fabrication classification (binning) that reflects the worst-case switching performance of a specific chip coming off the wafer. Even chips from the same wafer lot will have small transistor-level variations — some will reliably meet tighter timing margins than others. Chips that can do so are assigned a higher (faster) speed grade. ...

What Is a Critical Path? The critical path is the longest combinational logic path between any two registers in a synchronous digital circuit — measured in propagation delay. It sets a hard lower bound on your clock period: $$T_{clk} \geq T_{critical_path} + T_{setup} + T_{hold}$$ $$F_{max} = \frac{1}{T_{clk}}$$ Everything else in your design can run faster. The critical path is the single bottleneck that caps the maximum clock frequency. A Concrete Example 1 2 3 4 // Bad: long critical path always_ff @(posedge clk) begin result <= a + b + c + d + e + f + g + h; // 7 chained additions end What happens in a single clock cycle: ...

What Is Quantization? In signal processing, quantization is the process of mapping a continuous range of values to a discrete (integer) set. In deep learning and hardware acceleration, it specifically refers to: Converting floating-point (FP32, FP16, or BF16) model weights and activations to lower-bit integers (INT8, INT4, etc.) in order to reduce memory footprint and computational cost. Quantization is the bridge that makes neural networks practical on resource-constrained hardware. Why Quantization Is Essential for FPGA CNN Implementation FPGAs have a fixed amount of logic, DSP slices, and BRAM. Floating-point arithmetic is expensive in all three dimensions: ...

What Is LeNet-5? LeNet-5 is a convolutional neural network (CNN) proposed by Yann LeCun and colleagues in 1998 for handwritten digit recognition (the MNIST dataset). It is widely regarded as the historical model that established the foundational concepts of modern deep learning: convolution, pooling, and hierarchical feature extraction. LeNet-5 architecture as shown in (LeCun et al., 1998) MNIST — 70,000 greyscale 28×28 images of handwritten digits ...

If you have ever looked at an Ethernet frame in Wireshark and wondered why the 2-byte field at offset 12 is sometimes labelled “EtherType” and sometimes “Length”, this post explains the reason. 1. Ethernet II (also called DIX Ethernet) Origin: Defined jointly by DEC, Intel, and Xerox in 1980 — hence the alternative name “DIX Ethernet”. Frame structure: Field Size Meaning Destination MAC 6 B Target station address Source MAC 6 B Sending station address EtherType 2 B Upper-layer protocol identifier Payload 46–1500 B Network-layer packet FCS (CRC-32) 4 B Frame check sequence The 2-byte field carries an EtherType value — a number that directly identifies which protocol is encapsulated in the payload: ...

When implementing a network interface in RTL, you need a precise byte-offset map for every field in the frame. This post provides that reference for the most common combination: Ethernet II + IPv4 + UDP. Layer Stack [ Preamble (7B) + SFD (1B) ] ← handled by PHY/MAC, not in user datapath [ Ethernet II header ] [ IPv4 header ] [ UDP header ] [ Application data ] [ FCS / CRC-32 (4B) ] ← often stripped/added by MAC IP (configurable option in Xilinx TEMAC / Tri-MAC) Note: The preamble, SFD, and inter-packet gap (IPG) are inserted and stripped by the PHY/MAC layer and are typically not visible in the AXI-Stream user interface of a MAC IP core. ...