RTL

In FPGA and RTL development, four terms are frequently used to describe code changes: refactor, refine, fix/correct, and optimize. They are often used interchangeably in casual conversation, but they mean distinctly different things. Using the right term helps your team understand immediately what kind of change is being made — and whether to expect any behavioural differences. Refactor Definition: Restructure internal implementation without changing externally observable behaviour. A refactored module passes the same test vectors before and after the change. Simulation output is bit-identical. Timing may or may not improve. ...

When implementing a network interface in RTL, you need a precise byte-offset map for every field in the frame. This post provides that reference for the most common combination: Ethernet II + IPv4 + UDP. Layer Stack [ Preamble (7B) + SFD (1B) ] ← handled by PHY/MAC, not in user datapath [ Ethernet II header ] [ IPv4 header ] [ UDP header ] [ Application data ] [ FCS / CRC-32 (4B) ] ← often stripped/added by MAC IP (configurable option in Xilinx TEMAC / Tri-MAC) Note: The preamble, SFD, and inter-packet gap (IPG) are inserted and stripped by the PHY/MAC layer and are typically not visible in the AXI-Stream user interface of a MAC IP core. ...