FPGA Design

What Is a Critical Path? The critical path is the longest combinational logic path between any two registers in a synchronous digital circuit — measured in propagation delay. It sets a hard lower bound on your clock period: $$T_{clk} \geq T_{critical_path} + T_{setup} + T_{hold}$$ $$F_{max} = \frac{1}{T_{clk}}$$ Everything else in your design can run faster. The critical path is the single bottleneck that caps the maximum clock frequency. A Concrete Example 1 2 3 4 // Bad: long critical path always_ff @(posedge clk) begin result <= a + b + c + d + e + f + g + h; // 7 chained additions end What happens in a single clock cycle: ...