EasyFPGA

Custom RTL Design: TX & RX This is the first hands-on RTL episode. We translate the UART protocol specification directly into synthesizable SystemVerilog — starting from the mathematical relationship between clock frequency and baud rate, then building the TX FSM and RX center-sampling logic. Each design decision is derived from first principles so you can reproduce and modify it for any FPGA or baud rate. Design Requirements Target: 50 MHz system clock, 8E1 format ...

RS-232 & RS-485 When FPGAs communicate with external devices over UART, the signal rarely stays at 3.3V CMOS all the way to the destination. RS-232 defines an electrical standard for single-ended serial links up to 15 m, while RS-485 uses differential signaling to reach 1,200 m on a multi-drop bus. The most important lesson of this episode: UART is a logical protocol, and RS-232/RS-485 are completely separate physical standards that FPGA GPIO cannot directly drive. ...

UART Frame Format Each UART transmission carries data inside a precisely defined frame. Understanding the purpose of every field — not just its name — is what separates a developer who can implement UART from scratch from one who only configures a vendor IP. This episode dissects the frame bit by bit, covering the transmission order convention, parity computation, and the overhead implications of different format choices. UART Frame Structure Every UART transmission is based on a fixed Frame structure. ...

What is UART? UART — Universal Asynchronous Receiver/Transmitter A hardware communication protocol for serial communication between two devices. UART is one of the oldest digital communication protocols still in active use. Despite being designed alongside early teletype systems, it appears in virtually every FPGA board, microcontroller, and development kit — because it needs only two wires and every terminal emulator on every operating system speaks it. This episode covers the fundamentals: what asynchronous communication really means, how baud rate works, and why clock drift is the central engineering challenge when implementing UART from scratch. ...