Debug

An FPGA does not work in isolation. No matter how correct your RTL is, the design will fail if the power supply is noisy, the clock does not reach the device cleanly, or a digital interface is mismatched at the board level. FPGA engineers who can diagnose hardware problems are significantly more effective than those who can only debug RTL in simulation. This post covers the board-level skills that separate a junior FPGA engineer from a senior one. ...

https://www.amd.com/en/products/adaptive-socs-and-fpgas/intellectual-property/vio.html When debugging an FPGA, there are times when you need to modify settings or parameters and monitor internal signals in real time. Setting up communication interfaces, such as receiving input from switches and keys or using UART, can be a complex process. However, AMD FPGAs offer a solution with the Virtual I/O IP, which allows these tasks to be easily performed via JTAG. https://docs.amd.com/v/u/en-US/pg159-vio Xilinx Virtual Input/Output (VIO) is a soft IP core provided by Xilinx that allows you to monitor and control internal FPGA signals in real time using the Vivado Integrated Logic Analyzer (ILA) without needing physical I/O pins. ...

When debugging hardware using the Hardware Manager, the device connection is established after a delay following the initial boot. Once connected, you can configure trigger conditions and begin debugging. However, this delay means that the FPGA’s initial state cannot be examined using the Integrated Logic Analyzer (ILA), as it occurs before the device is accessible via the Hardware Manager. Illustrate a Hardware Manager connected to a device via JTAG, The Trigger At StartUp method enables you to define trigger conditions in the initial phase, immediately after the bitstream is downloaded and the system begins running. This allows you to debug the early stages of operation effectively. ...