DDR

Overview As parallel interfaces push to higher speeds, keeping all data bits synchronized becomes increasingly difficult. This post explains why global clock distribution hits a wall — and how source-synchronous signaling solves it. Signal Propagation on PCB Before diving into timing, it helps to understand how fast signals actually travel on a PCB: Typical propagation speed on FR4: 15–17 cm/ns A 1 cm trace length difference ≈ 60–70 ps of timing skew At 1 GHz (1 ns period), 70 ps of skew already consumes 7% of your entire timing budget from a single centimeter of mismatch. As data rates climb, this becomes unmanageable. ...

1. What Is a Parallel Interface? A parallel interface transmits multiple bits simultaneously across multiple data lines. As shown below, there are 8 to 32 or more data wires (D[7:0], D[31:0], etc.) between transmitter and receiver, along with a shared clock and control signals such as VALID and READY. ┌─────────────┐ ┌─────────────┐ │ Transmitter │ D[7:0] │ Receiver │ │ ├────────►│ │ │ │ CLK │ │ │ ├────────►│ │ │ │ VALID │ │ │ ├────────►│ │ └─────────────┘ └─────────────┘ Parallel Bus — 8 data bits transferred simultaneously each clock cycle ■ CLK ■ D[7:0] data ■ VALID Advantages: ...

FPGAs are optimised for massive parallelism, but their on-chip memory resources are limited. Block RAM (BRAM) and UltraRAM (URAM) are fast and easy to use, but they typically provide only a few tens of megabits to a few hundred megabits of capacity. When your application needs gigabytes — high-resolution video frames, machine-learning weight tables, large look-up tables — external DDR memory becomes essential. Why External DDR Memory? Memory Type Location Typical Capacity Bandwidth Access Latency Distributed RAM On-chip (LUT-based) < 1 MB Very high 1 cycle Block RAM (BRAM) On-chip (dedicated) up to ~200 MB High 1–2 cycles UltraRAM (URAM) On-chip (UltraScale+) up to ~500 MB High 2–3 cycles External DDR Off-chip (dedicated chip) 1–16+ GB Medium-High ~50–100 ns For applications such as: ...