CDR

In digital communication, data is represented as a binary bitstream of 0s and 1s. In practice, real-world data is rarely truly random — it often contains repetitive patterns, especially long runs of identical bits (e.g., ...000000... or ...111111...). At low speeds this causes no real harm, but at 1 Gbps and beyond, such patterns create critical signal integrity problems. At 1 Gbps, one bit period is just 1 nanosecond, so a run of tens or hundreds of identical bits means the signal voltage stays constant for a relatively long time. ...

The Limits of Parallel Buses Traditional parallel data buses were efficient at low clock rates, but as clock frequencies increased they ran into fundamental physical barriers. The core problem is timing skew: with many parallel data lanes plus a separate clock lane, each signal travels a slightly different path length on the PCB and through the package, arriving at the receiver at slightly different times. As the clock period shrinks, even a small skew becomes a significant fraction of a bit period, and data errors follow. ...