[태그:] FPGA
병렬에서 고속 SERDES까지, 그리고 Gigabit Transceiver
병렬 버스의 한계 전통적인 병렬 데이터 버스는 낮은 속도에서는 효율적이었지만, […]
High Speed Interface (10G, 100G) Guide
AMD FPGA 고속 인터페이스 설계 가이드 AMD FPGA 고속 인터페이스 […]
UART Parity Bit and Frame Structure
UART frames consist of a start bit, data bits, an optional parity bit, and stop bit(s). Parity can be even, odd, or omitted. Even parity is calculated by ensuring an even total of 1s. The receiver checks the parity bit against calculated values to detect errors, flagging discrepancies accordingly.
Why AMD(Xilinx) Recommends Synchronous Resets
https://docs.amd.com/r/2021.1-English/ug949-vivado-design-methodology/When-and-Where-to-Use-a-Reset Advantages of Synchronous Resets Benefit Explanation Better Resource Mapping […]
Understanding Active-Low Resets in HDL Design
In HDL design (such as Verilog or VHDL), an active-low […]
FPGA Implementation of RoCEv2
What is the RoCE v2? RoCEv2, or RDMA over Converged […]
Virtual Input/Output
https://www.amd.com/en/products/adaptive-socs-and-fpgas/intellectual-property/vio.html When debugging an FPGA, there are times when you […]