FPGA Design

What Is a Critical Path? The critical path is the longest combinational logic path between any two registers in a synchronous digital circuit — measured in propagation delay. It sets a hard lower bound on your clock period: $$T_{clk} \geq T_{critical_path} + T_{setup} + T_{hold}$$ $$F_{max} = \frac{1}{T_{clk}}$$ Everything else in your design can run faster. The critical path is the single bottleneck that caps the maximum clock frequency. A Concrete Example 1 2 3 4 // Bad: long critical path always_ff @(posedge clk) begin result <= a + b + c + d + e + f + g + h; // 7 chained additions end What happens in a single clock cycle: ...

FPGAs are optimised for massive parallelism, but their on-chip memory resources are limited. Block RAM (BRAM) and UltraRAM (URAM) are fast and easy to use, but they typically provide only a few tens of megabits to a few hundred megabits of capacity. When your application needs gigabytes — high-resolution video frames, machine-learning weight tables, large look-up tables — external DDR memory becomes essential. Why External DDR Memory? Memory Type Location Typical Capacity Bandwidth Access Latency Distributed RAM On-chip (LUT-based) < 1 MB Very high 1 cycle Block RAM (BRAM) On-chip (dedicated) up to ~200 MB High 1–2 cycles UltraRAM (URAM) On-chip (UltraScale+) up to ~500 MB High 2–3 cycles External DDR Off-chip (dedicated chip) 1–16+ GB Medium-High ~50–100 ns For applications such as: ...

https://docs.amd.com/r/2021.1-English/ug949-vivado-design-methodology/When-and-Where-to-Use-a-Reset Advantages of Synchronous Resets BenefitExplanationBetter Resource MappingSynchronous resets can be mapped directly to more FPGA resources (e.g., flip-flops inside DSPs, BRAMs).Improved Logic PerformanceAsynchronous resets can negatively affect general logic timing paths and increase routing complexity.Simpler RoutingA global asynchronous reset might not increase control sets but does require routing reset wires to many elements, which can become complex.Protects Memory StructuresAsynchronous resets may corrupt the contents of BRAMs, LUTRAMs, and SRLs during reset assertion—especially if those resources are driven by asynchronously reset registers.Placement FlexibilityWith synchronous resets, the logic can be more easily remapped during implementation for better packing and performance.Compatibility with Dedicated BlocksSome blocks like DSP48s and BRAMs only support synchronous resets, so using asynchronous resets can prevent proper inference into those blocks. ...

In HDL design (such as Verilog or VHDL), an active-low reset means the reset signal is enabled when it is low (logic 0). It is widely used in both ASIC and FPGA designs for several practical and electrical reasons: 1. Electrical Stability Logic low (0 volts, GND) is generally more stable and noise-immune than logic high (VCC). During power-up, signals tend to default to low due to internal pull-downs or the absence of a valid voltage, so using an active-low reset ensures that the system starts in a known, reset state. ...

https://www.amd.com/en/products/adaptive-socs-and-fpgas/intellectual-property/vio.html When debugging an FPGA, there are times when you need to modify settings or parameters and monitor internal signals in real time. Setting up communication interfaces, such as receiving input from switches and keys or using UART, can be a complex process. However, AMD FPGAs offer a solution with the Virtual I/O IP, which allows these tasks to be easily performed via JTAG. https://docs.amd.com/v/u/en-US/pg159-vio Xilinx Virtual Input/Output (VIO) is a soft IP core provided by Xilinx that allows you to monitor and control internal FPGA signals in real time using the Vivado Integrated Logic Analyzer (ILA) without needing physical I/O pins. ...

AXI stands for Advanced eXtensible Interface. It is a part of the AMBA (Advanced Microcontroller Bus Architecture) protocol family, developed by ARM. AXI is designed for high-performance, high-frequency system designs and is widely adopted in FPGAs and SoCs. Zynq SoC connects between Processing System (PS) and Programmable Logic (PL) Interconnection between Xilinx IP cores (e.g., Block RAM, DMA, TEMAC) Communication with MicroBlaze processor AXI Interconnect to connect multiple master/slave devices ...

When debugging hardware using the Hardware Manager, the device connection is established after a delay following the initial boot. Once connected, you can configure trigger conditions and begin debugging. However, this delay means that the FPGA’s initial state cannot be examined using the Integrated Logic Analyzer (ILA), as it occurs before the device is accessible via the Hardware Manager. Illustrate a Hardware Manager connected to a device via JTAG, The Trigger At StartUp method enables you to define trigger conditions in the initial phase, immediately after the bitstream is downloaded and the system begins running. This allows you to debug the early stages of operation effectively. ...

Effectively utilizing Vivado’s Text Editor can greatly assist in FPGA design. Let’s explore the advantages of the Text Editor in Vivado IDE (Integrated Development Environment) when developing AMD (Xilinx) FPGAs. **On-the-fly syntax checking: **Instant syntax check **Assistance with errors and warnings: **Markers in red or yellow appear on the right scroll bar. They allow you to navigate directly to the location of syntax errors or warnings. Additionally, you can hover (move the cursor over) to identify the specific error ...