Ethernet & Networking

If you have ever looked at an Ethernet frame in Wireshark and wondered why the 2-byte field at offset 12 is sometimes labelled “EtherType” and sometimes “Length”, this post explains the reason. 1. Ethernet II (also called DIX Ethernet) Origin: Defined jointly by DEC, Intel, and Xerox in 1980 — hence the alternative name “DIX Ethernet”. Frame structure: Field Size Meaning Destination MAC 6 B Target station address Source MAC 6 B Sending station address EtherType 2 B Upper-layer protocol identifier Payload 46–1500 B Network-layer packet FCS (CRC-32) 4 B Frame check sequence The 2-byte field carries an EtherType value — a number that directly identifies which protocol is encapsulated in the payload: ...

When implementing a network interface in RTL, you need a precise byte-offset map for every field in the frame. This post provides that reference for the most common combination: Ethernet II + IPv4 + UDP. Layer Stack [ Preamble (7B) + SFD (1B) ] ← handled by PHY/MAC, not in user datapath [ Ethernet II header ] [ IPv4 header ] [ UDP header ] [ Application data ] [ FCS / CRC-32 (4B) ] ← often stripped/added by MAC IP (configurable option in Xilinx TEMAC / Tri-MAC) Note: The preamble, SFD, and inter-packet gap (IPG) are inserted and stripped by the PHY/MAC layer and are typically not visible in the AXI-Stream user interface of a MAC IP core. ...

What is the RoCE v2? RoCEv2, or RDMA over Converged Ethernet version2 is a network protocol that enable Remote Direct Memory Access (RDMA) over standard Ethernet networks using UDP/IP. It’s designed to deliver high-throughput, low-latency communication while minimizing CPU usage-making it ideal for data centers, high-performance computing, and storage systems. The link below is a lecture on RDMA. It provides a lot of useful information. https://www.coursera.org/learn/the-fundamentals-of-rdma-programming/home/info RoCEv2 Packet Format Ethernet Header Standard Ethernet frame header. ...

In FPGA-based designs, Ethernet is commonly used as a communication interface with PCs. Whether for data transfer, debugging, or network-based control, Ethernet provides a flexible and high-speed connectivity option. To integrate Ethernet into an FPGA, the design typically consists of: MAC (Media Access Control) Layer: Handles frame encapsulation and transmission. PHY (Physical Layer) Interface: Manages signal-level modulation and transmission over the Ethernet medium. Higher-Level Processing: Can be implemented using embedded processors (such as MicroBlaze or ARM in SoC FPGAs) or custom hardware logic for protocol handling. ...